PLP technology roadmap toward high-end packaging fueled by AI

PLP is a cost-efficient solution for advanced packages manufactured today at the wafer level, explains Yole Group in its new Panel Level Packaging 2025 report. PLP solutions include WLCSP, fan-out, and 2.5D organic interposers.

Gabriela Pereira, Technology & Market Analyst, Semiconductor Packaging at Yole Group, said, apart from advanced packaging, PLP can replace traditional packaging technologies like lead frame QFN, addressing small, simple packages for applications like RF electronics components, power electronic modules, and MCUs. 

This new report on semiconductor packaging by Yole Group identifies and classifies PLP technologies and analyzes both high-end applications for AI and HPC6 and low-end trends replacing QFN in power and analog segments. Moreover, analysts provide a detailed PLP benchmark versus wafer-level packaging in terms of cost and area efficiency. They outline the major technology roadmaps and provide a detailed overview of the global and Chinese PLP supply chains. Forecasts are segmented by package type, technology type, carrier size, and material.

Fan-In PLP production ramped up in 2024, capturing about a third of the PLP market, while core Fan-Out and HD Fan-Out captured the remaining two-thirds. The UHD Fan-Out segment of PLP has not yet been commercialized, however Yole Group expects low-volume production to start soon, driven by AI/HPC and high-end PC.

Yik Yee Tan, Senior Technology & Market Analyst, Semiconductor Packaging at Yole Group, stated that indeed, we expect TSMC to start running some PLP prototypes in the next few years, as it has recently started developing the technology.

PLP players have been focusing on developing technology for one of the two segments: low-end fan-out/fan-in PLP or high-end fan-out PLP. In terms of revenue, high-end, large-size FOPLP is the largest driver in the PLP market.

Fueled by chiplets and heterogeneous integration, semiconductor package sizes will continue to grow in the coming years. High-end packages for servers and data center AI applications currently feature the largest package dimensions. Therefore, they incorporate large-sized IC substrates and different flavors of 2.5D interposers.

To achieve the desired system performance while remaining costefficient, the integration of more chiplets and memory is essential. However, as interposer sizes increase, fewer chips can be produced per wafer.

This trend pushes the industry to transition from silicon to organic interposers and reconsider the wafer-level packaging paradigm, potentially adopting larger carrier platforms like PLP. For a large package size of ~5.5x the reticle size limit, PLP can increase carrier area efficiency by more than 80%, whereas WLP only allows 45%.

In the Panel Level Packaging 2025 report, Yole Group’s analysts estimated that PLP for UHD FO packages could enable a cost reduction of 10% to 20%, depending on the panel size utilized.

Market metrics
* From about $160 million to more than $600 million, the PLP market points at a 27% CAGR during the 2024-2030 period.
* By 2030, high-density fan-out and ultra-density platforms will dominate the market in response to the AI push.
* Ecosystem: In 2024, the PLP market is led by Samsung Electronics, closely followed by STMicroelectronics. Following them, other companies, including PTI, SIPLP, ASE, etc., have market shares of less than 10%.
* PLP is a cost-efficient solution for advanced packages that are today manufactured at the wafer level, including WLCSP, fan-out, and 2.5D organic interposers. PLP can also be utilized to replace traditional packaging technologies like lead frame QFN.