The RISC Vs CISC debate-still valid or irrelevant?

The processor business, over the

years, has seen its share of technological and ideological arguments. None, however, come

close to the zealotry that the RISC vs CISC architecture debate inspires. Perhaps it stems

from the time and money invested by companies which support these architectures. The truth

lies somewhere in between. Processors run on instructions. CISC or Complex Instruction Set

Computer is a method of using rich complex instructions to get a job done. It also makes

programs for CISC easier to write. The catch, however, is that the greater the complexity

of the instruction set the more processor cycles it takes to execute. RISC or Reduced

Instruction Set Computer as a design seeks to do away with this complexity by using

simpler, smaller instructions.The idea originated from the fact that 20% of the

instructions in a computer do 80% of the work.

Gaining performance advantage

An elegant method that makes the

distinction clearer and is taught in computer architecture books is the Classic

Performance Equation, which states that the number of cycles per instruction multiplied by

the instruction cycle time equals execution time. A processor therefore can be speeded up

in three ways: use fewer instructions for a given task; reduce the number of cycles for

some instructions; or speed up the clock-which refers to the speed ratings we are all so

familiar with-to decrease cycle time. CISC attempts to reduce the number of instructions

for a program while RISC tries to reduce the cycles per instruction. Over the years, to

gain performance advantage, both sides have borrowed heavily from each other. Clock speeds

have increased and the attempt has always been to get closer to the ideal. Pipelining is a

method used to achieve that-a classic example of an original RISC concept that is now used

in CISC designs as well. Pipelining is a technique whereby the processor processes more

than one instruction at a time.

The four operational stages of a

processor-fetch, decode, execute and write-are executed in parallel. At a very basic

level, an Intel Pentium-II chip takes its complex instructions, breaks them up into

smaller chunks (a la RISC) and processes them in parallel. At the opposite end of the

spectrum, a supposedly RISC processor like the G3 used in Apple Macintosh systems actually

has more instructions built in than a Pentium-II! In reality very few RISC processors

remain loyal to the original design goals with the exception of Compaq Alpha and the SGI

subsidiary MIPS' RX000 line of processor cores. And that explains where the business is

headed as well. RISC because of its simpler design consumes lesser power and the die

size-the area in which all the transistors are packed-is typically smaller. It is

therefore ideally suited for embedded applications-which is where MIPS seems to be headed.

The simplicity of design also makes

RISC processors cheaper to produce but that argument does not stand when you're competing

with the sort of volumes that Intel produces. In terms of sheer performance, RISC has not

fared too badly. RISC processors till very recently have maintained a lead in floating

point (mathematical) performance required for graphics applications. Only now are CISC

designs matching that performance. In terms of sheer performance, according to an

Illuminata Inc report, Alpha followed closely by Hewlett Packard's PA-RISC come out on

top. Intel's 64-bit processor due in mid-2000 will take a year or two to equal that

performance level. What the above arguments show is that RISC designs will for the near

future exist in the high-end enterprise class systems and in embedded applications. But

RISC is significant for its impact on processor design in general-so much so that it is

difficult to classify a processor as true to either.