RISC-V will have more robust security than commercial ISAs, moving forward: Travis Lanier, Ventana Micro

Ventana Micro Systems Inc. was founded in 2018 to revolutionize the processor market by offering high-performance, extensible and secure compute chiplets. Designs are leveraged for use in custom platform solutions through the use of open standards such as the RISC-V architecture for our CPUs and UCIe/BoW die to die interconnects that work with the ecosystem of chiplet partners.

Travis Lanier, VP, Ventana Micro, tells us more. Excerpts from an interview:

DQ: Elaborate on Ventana’s business footprint in India.

Travis Lanier: Ventana has an established presence in India's tech hubs Whitefield area (Bengaluru) and Kothrud (Pune). Ventana’s engineering, sales, and business teams in India are all growing rapidly to meet the demand for Ventana’s RISC-V solutions. As Ventana’s reputation as a trusted partner grows it is being invited to give keynote talks at prestigious conferences, such as SemiconIndia chaired by India’s Prime Minister, Narendra Modi.

DQ: What is the current situation of the Indian semiconductor market and key priorities?

Travis Lanier: We see our RISC-V solution as ideally suited for Indian organizations in the current environment for three primary reasons:

• RISC-V, an open-standard instruction set architecture (ISA), gives Indian organizations strategic independence and flexibility, while substantially reducing dependence on foreign proprietary technologies;
• the technology offers significant cost savings because it eliminates hefty licensing fees or royalty charges; and
• the flexibility and openness of RISC-V can boost domestic manufacturing, increase employment opportunities, and potentially lead to breakthrough innovations in energy efficiency in the semiconductor space.

DQ: What are Ventana’s offerings for the Indian market, and its unique selling point?

Travis Lanier: Ventana is enabling Indian data centers and semiconductor startups to move to RISC-V in the realm of high-performance computing. This is significant because RISC-V ushers in a new era of rapid innovation freedom with an open ISA with domain specific extensibility developed within a worldwide community, compared to x86/Arm architecture which is controlled by a few companies.

Through many key leadership positions within RISC-V International, and software initiatives like RISE, Ventana has enabled RISC-V to address data center needs and is the first to introduce a RISC-V performance level that is competitive with the latest x86/Arm processors.

Our technology is easily leveraged being delivered as soft IP, compute chiplets, or integrated products with partner technology utilizing OPC/ODSA and UCIe chiplet standards. A full fledged ecosystem enables integration with Domain-Specific Acceleration (DSA) components to ensure highly optimized solutions can be created across a wide range of applications all enabled with Ventana RISC-V high-performance compute.

Ventana has helped pioneer chiplet integration standards to ensure that compute chiplet logical integration is the same as soft IP, without all the complexity to harden high-performance CPU IP saving over $100M and multiple years of development effort.

Focusing on ultra low-latency, Ventana is able to minimize any performance overhead of breaking a monolithic SoC into component chiplets. This, in turn, enables more degrees of freedom over the chiplet boundaries that can focus on better system composility, subsystem function vendor ownership, and the ability to leverage existing AMBA IP interfacing.

DQ: How is Ventana driving innovation in the sector via R&D?

Travis Lanier: Ventana is at the forefront of transitioning data centers to RISC-V, enabling rapid innovation through open ISA. We are playing pivotal roles in developing ISA standard within RISC-V International and have been integral in software initiatives like RISE.

Ventana introduced RISC-V performance levels competitive with x86/Arm processors, and our work with chiplet integration standards like UCIe and ODSA simplifies and accelerates chip development for Data Center, Automotive, 5G, AI, and Client applications. Lastly, Ventana recently introduced Veyron, the world’s first data center class RISC-V CPU product family offering the highest performance RISC-V processor running at 3.6GHz in 5nm.

The Veyron V1 efficient micro-architecture also enables the highest single socket performance among competing architectures and enables the technology to be used for energy efficient applications.

DQ: What is the road from x86 through SPARC, back to x86 to ARM to RISC-V?

Travis Lanier: If you go back to the 1980s and 1990s, x86 was rapidly evolving to include all the high performance features that had already been developed in mainframes and workstations. It was where the microprocessor action was happening, and there were multiple startups doing x86. NexGen would be a prime example.

That said, 64-bit x86 did not exist in products until 2003, so if you really needed to deal with large memory you had to look at other processor architectures such as SPARC. Fast forward a bit, and of course x86 goes 64-bit, so if you are doing a high performance consumer device at that point x86 would seem to be the way to go. Unfortunately x86 has many restrictions on what you can do with it and who can make designs with it.

If you look around in the mid 2000s, it was apparent that Arm, with its new business model, was on the rise. That was only 32-bit at the time, but we worked with them to develop a 64-bit Arm architecture which we were the first to take to the data center.

Unfortunately, in the end, the ISA was still owned by a single commercial entity whose interests were not always aligned with what you were trying to do. The idea of a standard ISA that multiple companies can implement is the correct one, it just needed to be an open standard rather than a closed commercial one.

We bring a wealth of experience bringing ISAs to maturity, and that is what we are doing right now with RISC-V.

DQ: How is Ventana catering to the demand of RISC-V in India?

Travis Lanier: Demand for Ventana’s Veyron solutions is driven by Indian organizations that are seeking to create high performance applications, including data center, automotive, 5G, AI, and client. They mostly want to unleash innovation, while reducing reliance on foreign technologies that require prohibitive licensing fees. They also benefit from the growing local ecosystem of developers and academic initiatives, such as IIT Madras's RISC-V processors.

Ventana provides a variety of engagement models to accelerate their efforts, including final packaged products, compute chiplets, and CPU IP.

DQ: RISC-V is not as secure as a closed instruction set architecture (ISA). What are your thoughts around this?

Travis Lanier: There is nothing about an open standard ISA that makes it inherently less secure than a proprietary ISA. In the end, a commercial ISA has to be published for anyone to use effectively similar to what you do with any standard. In fact, one could argue that more risks might lie in a proprietary ISA since there are typically secret backdoors that can be found and exploited by malicious actors.

There is a tremendous amount of research around RISC-V security given its open standard accessibility that is simply not possible with commercial ISA. It seems more plausible to argue that RISC-V will have more robust security than commercial ISAs moving forward.

Another aspect that is often overlooked is that different regions often have different security requirements, and this is where RISC-V shines. For example, security features unique to India can be added while maintaining compatibility with the base RISC-V ISA.

Ventana's Veyron V1 includes comprehensive RAS features and patented microarchitecture resilient to side-channel attacks. Also, Ventana is working toward Functional Safety (ISO2622) and Cybersecurity (ISO21434) certifications on the entire IP portfolio.

DQ: RISC-V processors require more memory to store the additional instructions needed to perform complex tasks. What are you doing to solve problems?

Travis Lanier: This might have been somewhat true in the early days of RISC-V, but is not really the case anymore. The Zc extension was ratified this April, and early benchmarks show that whatever gaps there were with other ISAs on code size have been mostly closed.

Other things that can be done to reduce code size is compiler optimizations. Ventana is actively engaged in the optimization of the GCC and LLVM compilers for RISC-V.

DQ: Will RISC-V ever replace ARM in embedded systems?

Travis Lanier: Like most ISAs that get a huge installation base, Arm will be around for a while. That said, RISC-V has already replaced Arm in many embedded designs. Most new large SoCs that include “hidden” microcontrollers that are not visible to the end user are already using RISC-V to some degree. This is helping that mature the toolchain, and getting engineers who were previously more comfortable with legacy ISAs more comfortable with RISC-V.

Expect this to explode in the coming years as RISC-V moves up the performance and more robust IP and tools become available.