Processor Control

Silicon technology is believed to continue its relentless evolution under
Moore's Law, and chips holding over 100 mn gates will be achievable with 65 nm
technology in the near future. Meanwhile, new nanostructures or nanodevices in
the scale of 0.1-10 nm are under intensive development. New challenges and
opportunities lie in frontiers like nanoelectronic processor and computer
systems design and CAD for nanoelectronic systems.

In 2005, the semi conductor industry will hold steady. Cellphone shipments
have slowed to 8%, but with 3 megapixel cameras coming, the cellphone is going
to become the consumer's number one digital camcorder, and all kinds of
video-chats will be possible. It might even become your digital TV. We will
continue to see double digit growth in India and China, the world's
fastest-growing, emerging markets.

During the 1980s we saw the beginning of client-server, the PC and the
Ethernet, which brought PCT into the enterprise. The 1990's became the era of
the PC and the cellphone. Microsoft Windows and 32-bit microprocessors became
the industry standards for computing. The development of low-cost modems, made
possible by advances in DSP technology, led to the Internet boom. We reached
another important milestone with the introduction of high quality, 3-dimensional
graphics and texture-mapping technology.

Chips of the new block

In any semiconductor industry there are two important aspects of the product
development: VLSI Design and Wafer Technology.

VLSI design: Chip architecture plays a significant role in performance. The
world has migrated from 8 bit architecture to 16 bit, then 32 bit and now to 64
bit architecture for X86 CPU. AMD has launched 64 bit technology for servers,
desktops and laptops.

Wafer Technology: This is another important aspect of the semiconductor
industry. Today, wafers for AMD microprocessors are produced at the Fab 30
facility in Dresden, Germany. AMD is on track to deliver 90-nm dual-core
products to add performance while limiting power consumption in the second half
of this year. With the introduction of copper at the 180-nm node, we are on
target to deliver low-k dielectrics, SOI and first-generation strained silicon
at 130 nm; and soon, second-generation strained silicon at 90 nm. The current 90
nm transistor generation features Lgate of 50 nm, SOI and a triple spacer.

As customer-centric innovation grows, so will the right technology.

Editorial Advisors -Anirudh Mathuria, Country Head, Sinett
Semiconductor India, and Sanjeev Keskar, Country Manager, AMD Far East
(India)