What does going vertical mean? The reference to “verticalization” or “going vertical” means different things to different players in the electronics spectrum.
For system companies, vertical integration is increasingly becoming an imperative to differentiate from competitors and to meet cost and time-to-market pressures. End consumer electronics companies such as Apple and Google are designing their own system architectures rather than buying “off the shelf” like they used to. Their system needs are so tightly defined and requirements for optimization are so unique that they are assembling huge engineering teams to create customized or semi-custom designs.
For semiconductor and EDA companies, vertical technologies refers to technologies such as FinFETs and 3D-ICs that can help customers manage the challenges of advanced node design and stay ahead of Moore’s Law. There are other vertical technologies like vertical NAND or V-NAND, Flash technology in the memory space which offers 128Gb density in a single chip (see Samsung’s August 2013 announcement about this).
FinFETs and 3D-ICs
To satisfy the demand for advanced mobile computing technologies, design tools and fabrication methodologies have undergone a “vertical” shift in the past few years. These include:
FinFETs: FinFETs emerged from foundries as test chips to help the industry keep up with Moore’s Law and with time-to-market requirements. The popularity of FinFETs, a new type of 3D transistor, owes to its promise of offering significant power and performance advantages compared to that of commonly used planar devices. Given the benefits, FinFETs are expected to be the go-to choice for advanced process nodes from 20nm and below as they will enable new generations of high-density, high-performance, and ultra-low-power systems on chip (SoCs) for future smartphones, tablets, and other advanced mobile devices.
3D-ICs with TSV: As demands accelerate for increasing density, higher bandwidth, and lower power, many IC design teams are looking towards 3D-ICs with through-silicon vias (TSVs). 3D-ICs promise “more than Moore” integration by packing a great deal of functionality into small form factors, while improving performance and reducing costs. 3D-IC packages allow for multiple heterogeneous die—such as logic, memory, analog, RF, and micro-electrical mechanical systems (MEMS)—at different process nodes, such as 28nm for high-speed logic and 130nm for analog. This provides an alternative to SoC integration, potentially postponing an expensive move to a new process node for all of the functionality developers want to place in a single package.
3D-ICs with TSVs are expected to have a broad impact on areas such as networking, graphics, mobile communications, and computing, especially for applications that require ultra-light, small, low-power devices. Specific application areas include multi-core CPUs, GPUs, packet buffers/routers, smartphones, tablets, netbooks, cameras, DVD players, and set-top boxes.
What is driving the verticalization trend in design?
For the most part, it is the mobile revolution and the evolution of networking. Mobile computing is rapidly growing as the de-facto platform through which the world accesses information and entertainment. A quick look at the statistics shows that the amount of mobile data traffic pegged at 1.5 exabytes per month in 2013 is soaring toward 15 exabytes per month by 2018. This surge and demand for increasing bandwidth as well as for devices with better performance and ever larger memory and power capacity, has fueled the “vertical” led innovation by EDA and semiconductor companies and the system manufacturers.
As we move towards the Internet of Everything era, where devices from refrigerators to cars will have the ability to communicate with each other, the requirement for bandwidth and performance from each chip is expected to multiply manifold. Continued advancement and verticalization of chip design and fabrication can enable semiconductor companies to up the pace of innovation, while simultaneously addressing the ever-shrinking time-to-market windows and tremendous profitability pressures.