Secure-IC, now part of Cadence, drives embedded cybersecurity innovation at Chiplet Summit 2026

As chiplet-based architectures transform advanced semiconductor design, security becomes a core enabler of performance, scalability, and interoperability. The Third Annual Chiplet Summit brings together the ecosystem driving this modular shift, where trust across heterogeneous components is essential.

Secure-IC addresses the security challenges specific to chiplet-based systems, from secure inter-chiplet communication to trusted data exchanges across disaggregated architectures. At the Chiplet Summit, Secure-IC will highlight its embedded cybersecurity technologies, including the Securyzr integrated Secure Element S500 neo, designed for modular semiconductor environments and aligned with ARM Chiplet System Architecture (CSA) requirements.

Securing Chiplet-Based Architectures with Post-Quantum Cryptography, will be presented by Sylvain Guilley, CTO and Co-Founder of Secure-IC.

Abstract
Chiplet-based architectures are reshaping semiconductor design by enabling scalability, cross-foundry integration, and faster time-to-market. Yet, this modular approach also introduces critical security challenges: each chiplet must be trusted, authenticated, and resilient throughout its lifecycle. 

Without robust protection, a single compromised component can undermine the integrity of the entire system-in-package. This presentation will explore how Post-Quantum Cryptography (PQC) provides a foundation for long-term trust in heterogeneous chiplet ecosystems. 

Using the case study of the industry's first Arm-based system chiplet by Cadence, secured with integrated IP from Secure-IC, we will demonstrate how PQC-ready mechanisms, alongside secure boot, trust propagation, and remote attestation, establish resilient and standards-compliant chiplet systems. 

Attendees will gain insights into designing quantum-resistant SoCs for automotive, AI, and data center applications.