NEO Semiconductor intros world's first X-HBM architecture for AI chips

NEO Semiconductor, a leading developer of breakthrough memory technologies, has introduced the world's first extreme high-bandwidth memory (X-HBM) architecture for AI chips.

Built to meet the growing demands of generative AI and high-performance computing, X-HBM delivers unmatched performance with a 32K-bit data bus, and potentially 512 Gbit per die, dramatically surpassing the limitations of traditional HBM with 16X greater bandwidth or 10X higher density.

"X-HBM is not an incremental upgrade, it's a fundamental breakthrough," said Andy Hsu, Founder and CEO of NEO Semiconductor. "With 16X the bandwidth or 10X the density of current memory technologies, X-HBM gives AI chipmakers a clear path to deliver next-generation performance years ahead of the existing roadmap. It's a game-changer for accelerating AI infrastructure, reducing energy consumption, and scaling AI capabilities across industries."

Built on NEO's proprietary 3D X-DRAM architecture, X-HBM represents a major leap in memory technology by eliminating long-standing limitations in bandwidth and density. In contrast, HBM5, still in development and expected to reach the market around 2030, is projected to support only 4K-bit data buses and 40 Gbit per die.

A recent study from the Korea Advanced Institute of Science and Technology (KAIST) projects that even HBM8, expected around 2040, will offer just 16K-bit buses and 80 Gbit per die. In comparison, X-HBM delivers 32K-bit buses and 512 Gbit per die, allowing AI chip designers to bypass a full decade of incremental performance bottlenecks associated with traditional HBM technology.

Key features and benefits

Scalable – Enables faster data transfer between GPUs and memory for more efficient AI scaling.
High-performance – Unlocks untapped GPU capabilities to boost AI workloads.
Sustainable – Reduces power and hardware needs by consolidating AI infrastructure.