Breker and Frontgrade Gaisler ally on high-reliability RISC-V fault tolerant processor core

Breker Verification Systems has confirmed its RISC-V functional verification solutions were pivotal for verification of the NOEL-V, one of Frontgrade Gaisler’s fault-tolerant RISC-V processor IP cores.

“The development of Frontgrade Gaisler’s IP cores is guided by a philosophy that does not tolerate design issues,” notes Jan Andersson, Director of Engineering at Frontgrade Gaisler. “This demands the most robust verification environment, something Breker’s verification solution has contributed to improve, with its broad range of tests and in-depth corner case coverage.”

The ultra-high verification coverage afforded by Breker’s RISC-V SystemVIP and Test Suite Synthesis technologies make it a key technology in Frontgrade Gaisler’s development program. Breker provides test suites for the complete verification of RISC-V cores and SoCs from detailed microarchitectural analysis to advanced system integrity validation.

The NOEL-V processor by Frontgrade Gaisler, targets high-reliability applications, with its high-performance and fault-tolerant design. Built on the RISC-V architecture, NOEL-V offers customization options, allowing SoC designers to create solutions tailored to their specific needs. The processor is at the heart of the GR765, Frontgrade’s next generation radiation-hardened space microprocessor.

“We are delighted to work with Frontgrade Gaisler to achieve their extreme coverage goals and eliminate unpredictable corner cases, necessary given the extreme environments in which their devices are deployed,” says David Kelf, Breker’s CEO. “Our RISC-V test suites have become an essential component in over 20 commercial entities and other organizations development flows, providing us with unique experience of the numerous unusual verification issues inherent in these processors.”

Breker extended testing to target advanced, system-level integrity, in addition to its existing test suites and generators focused on instruction set architecture testing, included in its RISC-V SystemVIPs. It provides coverage by driving cross functional stress verification and unpredictable corner case discovery with its test suite synthesis technology applied across the verification flow from simulation, through emulation and prototyping to post silicon validation.