AGC participating in "JOINT3" Consortium to develop next-gen semiconductor packaging

AGC Inc. has joined the "JOINT3" Consortium to develop next-generation semiconductor packaging.

JOINT3 is a co-creation evaluation framework established by Resonac, with the aim of accelerating the development of materials, equipment, and design tools optimized for panel-level organic interposers through collaboration among material, equipment, and design companies.

JOINT3 brings together global leaders in semiconductor supply chain. Using a prototype line for 515 x 510mm panel-level organic interposers, the consortium promotes the development of materials, equipment, and design tools optimized for panel-level organic interposers.

In recent years, packaging for back-end processes have emerged as a key technology in the field of next-generation semiconductors. This includes 2.xD packages, whereby multiple semiconductor chips are arranged in parallel and connected via interposers, demand for which is expected to grow in line with the need for increased data communication capacity and speed.

As semiconductor performance improves, interposers are becoming larger, and there is a shift from silicon interposers to organic interposers made from organic materials. 

Conventional manufacturing methods involve cutting rectangular pieces from circular wafers. However, as interposers increase in size, the number of them that can be obtained from a single wafer decreases, posing a significant challenge.

To address this issue, a manufacturing process that transitions from circular wafer shapes to square panel shapes is gaining attention, as it allows for an increased number of interposers to be produced from a given area of wafer.

In JOINT3, AGC will leverage its diverse material technologies, including inorganic materials such as glass, as well as organic materials and their combinations, to provide innovative and high-quality glass carriers and interposer glass products.

By closely collaborating with participating companies, AGC aims to contribute to the establishment of panel-level process technologies, which are expected to become the foundational technologies for next-generation semiconductor packaging, and to promote their adoption as the de facto standard.