Advantest unveils SiConic test engineering for debug and validation

Advantest Corp. has unveiled SiConic Test Engineering (TE), the newest addition to the SiConic family introduced in February 2025. SiConic TE offers test engineers the ability to bring up and validate structural and functional tests over high-speed I/O (HSIO) interfaces in a scalable bench environment, enabling earlier validation and debug without occupying valuable ATE systems.

SiConic Link flexibly connects to standard evaluation boards through functional interfaces like USB, PCIe, control interfaces, and GPIOs. This is the foundation for SiConic TE to enable test engineers to rapidly validate and debug design verification (DV) and design for test (DFT) content in SiConic’s unified environment on the bench.

Building on the V93000 test system’s leadership in scan over USB or PCIe, SiConic’s unified environment brings native DV test content to test engineering without the error-prone and lengthy conversion and debug cycles typical for bring-up of advanced functional tests on ATE. 

Required for high-quality coverage in verification and test, functional testing enables a productivity boost for the bench collaboration of DV, DFT and test engineering. SiConic TE accelerates time-to-quality for both the V93000 and Advantest’s system-level test (SLT) and burn-in platforms with the ActivATE360 suite of software tools.

Integrating seamlessly with SiConic Link hardware and the SmarTest 8 software platform, SiConic TE provides users with comprehensive access to functional HSIO links for enhanced throughput and rich trace capabilities during test execution. By enabling smoother handoffs between silicon validation (SV), DV and TE teams, SiConic TE fosters tighter cross-domain collaboration.

Through its unified test environment and shared ecosystem, SiConic TE improves the correlation between bench, ATE and SLT systems. The tool’s optimized engineering resources allow bring-up and debug to be offloaded from ATE to the bench, freeing up valuable tester capacity and enabling more effective scaling. 

In addition, tight integration with leading EDA partners enables cross-functional collaboration with DV and DFT teams, improving test content development and speeding first-silicon success.

“With SiConic Test Engineering, we’re expanding the SiConic vision to empower test engineers in a unified environment on the bench,” said Juergen Serrer, CTO and Executive VP, SoC Test Business Unit, Advantest. 

“By moving bring-up and validation to scalable bench environments—and keeping DV, DFT, SV, and TE aligned through a scalable ecosystem—we’re helping customers validate faster, collaborate smarter, and maximize their engineering resources.”

According to G. Dan Hutcheson, Vice Chair, TechInsights: “Improving productivity at the R&D level is vital for design engineers. Advantest’s automated silicon validation approach would allow sign-off and test engineering to proceed concurrently using shared test data, helping ramp SoC designs more quickly, and shortening time-to-money, while ensuring design-to-system quality.”