By Dr. Chris Rowen, Fellow and CTO of IP Group, Cadence
When you’re considering the electronic design ecosystem, you may not make a ready association with the world of mammals and insects. But think more deeply about the topic, and there are some obvious parallels. Specifically, the diversity of the design ecosystem is exploding now and chip architectures are bifurcating into a world of “mammals” (where there are roughly 5,000 species) and “insects” (which number in the millions). Translated into the electronics world, the mammals here are general-purpose, high-performance electronics platforms like cellphones, PCs, and servers, while the “insects” are represented by a diverse array of low-power, highly application-specific chips for domains like the Internet of Things (IoT), consumer devices, and wearables.
Like mammals in the animal kingdom, the general-purpose chips have lots of smarts and lots of versatility. They use a multitude of processors—CPUs, DSPs, and GPUs—to address complex environments where adaptability is essential to survival.
But these chips are bigger, take more power, and take longer to develop. By contrast, when you think about the insect world, there’s a staggering diversity of types that are very focused on their niche and also power efficient, much like application-specific chips. These chips also use processors to provide some adaptability, but these brains are much smaller and lower power, often with a high degree of specialization to the tasks at hand in their narrower ecological niches.
This diversity of the “insects” platforms is good news for SoC and system designers and for electronic design automation. It suggests that SoC design may bifurcate into distinct IP, tool flows, and silicon nodes for general platforms and for special data-intensive, ultra-low power devices (the “insects”). As a result, SoC design starts for the “insects” may increase substantially.
Much of this acceleration in design opportunity stems from the dramatic increases in data capture and transmission that are fueling many of our applications today, from social networking to smarter cars, appliances, medical devices, and security systems. The proliferation of motion sensors, microphones, and image sensors is creating huge new streams of data to capture, communicate, and analyze, as well as a fantastic new variety of products. The increased data-processing requirements drive a need for both lower energy consumption and higher compute rates for the end devices.
Cognitive Layering Offloads the Host Processor
As the electronics community builds more and more platforms that must be both highly energy efficient and highly capable, one particular architecture technique is emerging as the most essential—cognitive layering.
This idea is based on having different levels of the whole software system run on different processors, with the lowest power and most specialized offload processors at the bottom of the stack and the most general-purpose, highest power processors at the top of the stack. This layering may be fully implemented in a single chip, with general-purpose CPUs on top, offloading work to DSPs and GPUs, which in turn offload even more specialized tasks to narrowly dedicated, but still programmable, engines.
Alternatively, the layer can be seen across distributed hardware that now implements our electronic world, with general-purpose cloud-based servers working with more specialized cloud-edge or gateway boxes, which connect to still more specialized IoT devices.
The total application is effectively distributed across these layers, leveraging the high efficiency of the IoT device, along with the general compute horsepower and data access of the cloud server.
The nature of the smallest devices results in some consequences for many SoCs—namely that to support these types of designs, the highest volume SoCs usually have a mandate for alertness—they need always-on functionality. To save power, most of the chip must be turned off most of the time, but the system must maintain the impression that they are always on.
Using a cognitive layering approach, you can direct an appropriate processing engine to address layers or states of a processing task. As a result, you can offload the host processor in your design with a low-power, always-on DSP. In Figure 1, we can see that each layer has just enough processing to support the level of alertness required by the system at that given point. Such a parallel processing architecture can improve latency, energy, and throughput.
There are many application domains that can make use of cognitive layering—inertial navigation, computer vision, interface to real-time sensors and actuators, interactive graphics, and local wireless communications are just a few examples where we can see dramatic performance and energy improvements.
Electronic design in the IoT era will mean less worry over the demise of Moore’s Law and, instead, more focus on application creativity over raw transistor count. The data that our devices and applications are collecting will continue to be converted into useful insights—this push for intelligence will drive computing.
Moreover, this volume of data is also driving a design bifurcation into very low- energy, small footprint, and very high-speed memory protocols and devices, often with much larger memory footprints.
As shown in Figure 2, successful designs for applications such as wearables, smart home systems, and medical devices will rely on extreme-fit SoCs that leverage on-chip memory. General-purpose system platforms, on the other hand, will continue to rely on extreme-scale SoCs with off-chip memory. A closely integrated design flow that spans system architecture, software and processor configuration, digital/analog block design, design verification, and system integration will become even more important.