semiconductor

Cadence announces ML-based tool Cerebrus to automate chip design

Cerebrus uses unique ML technology to drive the Cadence RTL-to-signoff implementation flow, delivering up to 10X productivity and 20% PPA improvements for implementation.

Cadence Design Systems announced the delivery of the Cadence Cerebrus Intelligent Chip Explorer, a new machine learning (ML)-based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals. The combination of Cerebrus and the Cadence RTL-to-signoff flow offers advanced chip designers, CAD teams and IP developers the ability to improve engineering productivity by up to 10X versus a manual approach while also realizing up to a 20% better power, performance and area (PPA).

With the addition of Cerebrus to the broader digital product portfolio, Cadence offers the industry’s most advanced ML-enabled digital full flow, from synthesis through implementation and signoff.​ The new tool is cloud enabled on Amazon Web Services (AWS) and other leading cloud platforms and utilizes highly scalable compute resources to rapidly meet design requirements across a wide range of markets including consumer, hyperscale computing, 5G communications, automotive and mobile.

Cerebrus provides customers with the following benefits:

  • Reinforcement ML: Quickly finds flow solutions human engineers might not naturally try or explore, improving PPA and productivity.
  • ML model reuse: Allows design learnings to be automatically applied to future designs, reducing the time to better results.
  • Improved productivity: Lets a single engineer optimize the complete RTL-to-GDS flow automatically for many blocks concurrently, allowing full design teams to be more productive.
  • Massively distributed computing: Provides scalable on-premises or cloud-based design exploration for faster flow optimization.
  • Easy-to-use interface: Powerful user cockpit allows interactive results analytics and run management to gain valuable insights into design metrics.

“Previously, design teams didn’t have an automated way to reuse historical design knowledge, leading to excess time spent on manual re-learning with each new project and lost margins,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “The delivery of Cerebrus marks an EDA industry revolution with ML-driven digital chip design where engineering teams have a greater opportunity to provide higher impact in their organizations because they can offload manual processes. As the industry continues to move to advanced nodes and design size and complexity increase, Cerebrus lets designers achieve PPA goals much more efficiently.”

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