Cadence and Samsung Foundry Enhance AI and 3D-IC Chip Innovation

Cadence Design Systems, Inc. (Nasdaq: CDNS) announced a significant collaboration with Samsung Foundry focused on advancing design technology for AI and 3D-IC semiconductors. This partnership aims to address the demands of various high-tech applications, including AI, automotive, aerospace, hyperscale computing, and mobile, by leveraging Cadence’s digital and analog tools optimized for Samsung Foundry's advanced node SF2 gate-all-around (GAA).

Key Developments from the Collaboration

1. Leakage Power Reduction with Cadence.AI: Utilizing the Cadence® Cerebrus Intelligent Chip Explorer, Cadence and Samsung have achieved over a 10% reduction in leakage power on the SF2 GAA platform. This has been demonstrated with a test chip developed in collaboration with a mutual customer.

2. Certification of Cadence Backside Implementation Flow: Cadence’s RTL-to-GDS flow, including various solutions such as the Genus™ Synthesis Solution and Innovus™ Implementation System, has been certified for Samsung’s SF2 node. This certification validates the flow's readiness for advanced design development, incorporating features like backside routing and nano TSV insertion.

3. Support for Multi-Die Integration: The Cadence Integrity™ 3D-IC platform is now enabled for all of Samsung's multi-die integration offerings. The platform includes early analysis and package awareness features compliant with Samsung’s 3DCODE 2.0. Additionally, thermal warpage analysis and system-level LVS support have been integrated to enhance the design process.

4. Analog Circuit Process Migration: Cadence’s AI-powered Virtuoso Studio has facilitated rapid retargeting and circuit optimization, significantly improving turnaround times. A reference flow for FinFET-to-GAA analog design migration has also been established with successful experimental results.

5. mmWave RFIC Design Flow Success: A 48GHz power amplifier design has been successfully taped out using Cadence’s mmWave RFIC design flow. This validates the robust system reference flow for passive device creation, EM extraction, and post-layout verification.

6. Physical Verification Flow Certification: Cadence’s Pegasus Verification System is now certified for Samsung Foundry's 4nm and 3nm process technologies. This system integration into Cadence Virtuoso Studio offers improved signoff quality and faster turnaround times for advanced nodes.

7. Advanced IP Portfolio: Cadence has developed an extensive IP portfolio on Samsung's SF5A and other advanced nodes, supporting various high-performance applications with PHY IP for standards like PCIe® 6.0 and GDDR7 memory.

8. Advanced Verification for AI: Samsung Foundry has applied Cadence’s advanced verification technologies, including the Palladium Enterprise Emulation System and JasperC, to manage the complexity of AI chip design and meet time-to-market goals for SF3.

Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence, said: “We are honored to partner with Samsung, a true example of a chips-to-systems company, to bring this technology for our joint partners to design the next generation of intelligent systems. The hyperconvergence of AI with modern accelerated compute requires a strong silicon infrastructure. With these new AI-powered, certified design flows and standardized solutions, mutual customers can confidently design for Samsung advanced nodes while achieving their design and time-to-market goals.”

Sangyun Kim, Vice President and head of Foundry Design Technology Team at Samsung Electronics, said: “Samsung and Cadence have a close collaboration to advance technology and help our customers deliver competitive designs to the market efficiently. Our joint efforts enable customers to utilize Samsung’s latest process and technology innovations to push the limits for the most advanced AI, hyperscale computing and mobile SoC designs.”